Pre-University Examination
Digital Logic Design
Time: 3
Hours Max Mark : 100
Note:-
Attempt All Question
1. Attempt
any four.
(a).Represent
decimal 5137 in the 2421 code. Show that the code is self-complementation and
perform 954+469 BCD numbers and also show the necessary steps for their sum.
(b).Explain
singed binary no and the range of 16 bit unsigned no, 16 bit signed one’s
complement no and the range of 16 bit singed 2’s complement number.
(c).Simplify
the following function using tabulation method implements the reduced function
using NAND gates only.
F(A,B,C,D,E)=∑M(0,1,3,5,6,9,11,14,21,23,24,31)+∑d(25,30)
Assume both
normal and complement inputs are available.
(d).
Simplify the following expression to SOP and POS form both------
(I). (A+C+DI)(AI+B+DI)(AI+BI+DI)(AI+B+CI)
(II). ACDI+CID+ABI+ABCD
(e). Explain
how does parity help in error detection? Given the 8-bit data word 01011011, generate
the 13-bit composite word for the hamming code that corrects single errors and
detects double errors.
(f). Explain
the floating point data representation for decimal no. and binary number when
it a floating point number said to be a normalized. Represent the no. (46.5)10
as a 32-bit floating binary number.
2. 1.
Attempt any four.
(a).
Describe look ahead carry adder.
(b). Explain
priority encoder and design a four input priority encoder but with input D0
having the highest priority and input D3 the lowest priority.
(c). Design
a code converter that converts a decimal digit from the 8,4,-2,-1 code to BCD.
(d). A binary
multiplier multiplies two unsigned 4-bit number. Design the circuit using AND
gates and binary adders.
(e). Show
that a full subtracter can be constructed with 2 half subtracter and an OR gate
and Implemented full adder with two 4×1 MUX.
(f).Construct
a 5:32 decoder with 4 3:8 decoders with enable and a 2:4line decoder.
3. Attempt
any four.
(a). What is
race around condition in JK latch? How to avoid it. Draw and explain the
working of master slave J-K flip flop.
(b). Explain
shift register its application & universal shift register.
4. Attempt any two.
(a). Explain
in brief the ASM chart. Explain how the ASM chart differ from a state diagrame.
Show the 8
exit paths in an ASM block emanating from the decision boxes that check the 8
possible binary values of 3 cntrol variables x,y,z.
(b). Draw
the ASM chart for a circuit with two 8-bit register RA,RB that receive two
unsigned binary numbers that perform the subtraction operation RA-RB→RA use 2’s complement method for subracctio
and set a borrow to 1 if answer is negative.
(c). what is PLA? How is differ from
ROM. List PLA programming table for the BCD to excess-3 code converter.
5. 1. Attempt any tow.
(a). Explain
what is hazards & different types of Hazards, how hazards occure in
combination circuit.
(b).
(i). Explain
the difference between asynchronous and synchronous sequential circuit.
(ii). Define
fundamental –mode operation.
(iii).
Explain the difference between stable and unstable state.
(iv).What is
the difference between an internal state and a total state?